By Frederik De Swaef, Field Applications Engineer, Macronix and Francesco Petruzziello, MCU Product Application Engineer, NXP Semiconductors
The modern 32-bit microcontroller is a remarkably capable device, but its abilities have given rise to a problem for the design engineers who use them: faced with ever-growing demand for more features, such as more detailed graphics or a greater range of languages to be supported in the user interface, designers are finding themselves limited by the small size of the typical MCU’s on-chip Flash memory.
Today, 32-bit MCUs are normally supplied with an on-chip Flash memory no larger than 1Mbyte. And the options for extending this on-board memory have changed in recent years: it is now rare to add external parallel Flash, since few MCUs support the parallel external memory interface. One of the reasons for this lack of support is the number of pins a parallel Flash needs for a 8- or 16-bit data bus and 20 or more address and control lines.
SPI NOR Flash is another option that the design could consider, but this memory type is much slower than on-chip and parallel Flash. Further, it is normally impossible to execute code from SPI Flash and even if it is possible, the performance is poor.
To solve this problem of adding external Flash memory, NXP Semiconductors has developed a new, easy-to-use external memory interface. Called SPI Flash Interface (SPIFI), it is intended for use with the popular Quad SPI NOR Flash memory type, which is cost-effective and provides a wide choice of densities.
SPIFI is available today in NXP’s LPC1800 family of ARM® Cortex®-M3 MCUs and in the LPC4000 and LPC4300 families of ARM Cortex-M4 MCUs. SPIFI support will be added to more NXP MCUs in future. SPIFI support means that these controllers can benefit from the proven Quad SPI memory technology provided by the MX25 range of serial NOR Flash devices from Macronix. These range in size from 8Mbits to 512Mbits, and are suitable for both fast data storage and in-place code execution.
Quad SPI is a modified serial peripheral interface which is capable of communicating on four data lines; traditional SPI uses only a single line. This multiplies the data throughput by almost four times, and makes high-performance execution in place possible. Compared to parallel NOR Flash with a 16-bit data bus, Quad SPI NOR Flash can achieve almost twice the total throughput, as shown in Figure 1.
|Interface||Mode||Access Time (nS)||Effective Throughput (MB/s)|
*Effective access time
Throughput is not Quad SPI’s only advantage: requiring only six connections between the MCU and the memory IC, routing is far less complex than that of a parallel Flash design, which calls for between 30 and 45 tracks.
Macronix Quad SPI Flash choices
The MX25 series of Quad SPI Flash memories from Macronix is available in various small 8- and 16-pin packages. These SOP, WSON and USON devices have a very small board footprint. Macronix produces MX25 devices with different memory densities in the same footprint or a compatible footprint, so that OEMs can migrate from one density to another without making any changes to board layout. Only when migrating to a density higher than 128Mbits does the designer have to implement minor software changes to support 4-byte addressing.
In NXP MCUs, the SPIFI interface is directly connected to the ARM core’s AMBA High-performance Bus (AHB), which means that the Quad SPI Flash is mapped and accessible for transfer via I/O or DMA channels, as shown in Figure 2. When executing in place, instructions are loaded into the SPIFI buffers directly from the external Flash, with no software overhead.
The Quad SPI Flash itself is controlled by five registers. These registers set the configuration and commands for reading and retrieving status information, and are transparently used by the on-chip ROM driver and the SPIFI library. They can also be directly accessed by the user application if desired.
The MCU’s SPIFI hardware controls the process for reading from the Quad SPI Flash. If code is stored there, the hardware will fetch it automatically in accordance with the register settings, with no software intervention. Initiation of writing and erasing operations is controlled by software settings.
The commands for data transfer have the same structure as those of a conventional SPI Flash memory; they specify the command, address and data for reading and writing, as shown in Figure 3. With Quad SPI Flash, the command will be sent on one line, and the address on four lines. Data are also moved from Flash on four lines. The use of four lines means that sending a 24-bit or 3-byte address requires only six clock cycles, instead of 24 in an SPI Flash memory. Similarly, 1 byte of data is received in two clock cycles instead of eight.
The Macronix MX25 Flash memories are capable of running at a clock frequency up to 104MHz during all operations. For read operations, the designer must take into account the need for dummy cycles after transferring the address when calculating the access time required to fetch the first byte. After the first byte, the address will automatically be incremented and data will be sent out with no additional access time until the Select pin goes high again. This enables a fast data throughput when reading sequential data.
Random read operations, such as branching in instructions, must use the Enhanced Read mode. This mode enables data to be read without sending a Read command. The address alone needs to be provided, saving eight clock cycles. The Enhanced Read mode is set by toggling bits in the dummy cycles of the first read operation. All subsequent reads only need to transmit the address.
NXP MCUs’ support for Quad SPI Flash Some NXP ARM Cortex-M MCUs have no on-chip Flash memory. This includes the LPC1810, LPC1820, LPC1830 and LPC1850, and also the LPC4310, LPC4320, LPC4330, LPC4350 and LPC4370. All these devices, however, can use external Quad SPI Flash as their sole nonvolatile memory for data and code storage and for in-place execution, enjoying outstanding read and write performance.
The Macronix MX25Lxxx35E/F series is ideal for this, offering densities from 8Mbits to 512Mbits 64Mbytes in 8-pin or 16-pin packages, as shown in Table 2. The designer has the flexibility to migrate during development without being tied to one density, while benefitting from high performance combined with a very low bill-of-materials cost.
SPIFI is also implemented in LPC MCUs which do feature on-chip Flash. In this case, the function of the Quad SPI external Flash is to extend the on-chip memory, providing extra code- or data-storage capability.
|Density||MX IC Type||EPN||Package|
Table 2: Macronix offers a broad choice of Quad SPI NOR Flash memories
This is often required in Graphical User Interfaces (GUIs). Traditionally in these applications, the image data are stored in an external SPI or parallel Flash, with the disadvantages described above. Data often needs to be shifted from the external device into internal or external RAM, and then moved again to the display itself. This means that the data have to be moved twice before being displayed.
The high throughput of the MX25 Quad SPI Flash and the memory mapped SPIFI interface allow data to be shifted directly from external Flash to the display: Now, the data are moved only once and the amount of RAM needed as well as the memory bus load can be markedly reduced.
When a 32-bit MCU has no on-chip Flash memory, or its on-board Flash is not large enough, the ideal solution is to add a Quad SPI external Flash memory. Quad SPI Flash supported by the SPIFI interface implemented in NXP ARM Cortex-M MCUs removes the complexity of designing with external parallel Flash, reducing pin count and offering better performance. This makes the combination a good choice for many applications in industrial equipment, consumer devices and white goods.