In developing the ECP5TM FPGA family, Lattice breaks the rule that all FPGAs should be the highest density, power hungry, and expensive. With a focus on compact, high volume applications, Lattice optimized the ECP5 architecture for low cost, small form factor and low power consumption. These characteristics make the ECP5 devices ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs.
2x resource improvement with unique DDR mode
2x resource improvement for symmetrical filters
Key Features and Benefits:
- Cost Optimized Architecture
– Focused on providing best value below 100K LUTs.
– Smart ball depopulation simplifies package integration with existing PCB technology.
– Double Data Rate capability improves DSP block utilization.
- Small Packages with High Functional Density
– 85K LUTs in 10×10 mm, 0.5 mm pitch package with SERDES.
- Low Power Consumption
– Single channel SERDES functions below 0.25W.
– Quad channel SERDES functions below 0.5W.
July 15, 2014 – 10:00am – 11:30am
Click here to register for the webinar. This webinar is in Chinese.